During semiconductor device fabrication, defects may be present due to process abnormalities. In general, defects are the result of material being formed where it should not be or material being absent where it should be. As chip feature sizes shrink further, these defects have become more complex and more difficult to detect during testing.
Traditionally, these defects have been logically represented in scan testing by “faults.” The faults can be modeled at various levels of design abstraction. Two known and commonly used fault models are stuck-at-0 (SA0) and stuck-at-1 (SA1) fault models. During testing, a fault is detected when a particular test pattern activates or sensitizes the integrated circuit to the fault and makes the error observable. However, current scan test methodologies use a very limited set of fault models which do not characterize the defect behavior of the integrated circuit completely. Therefore, a large percentage of faults may be undetected by testing and result in unpredictable circuit behavior.